Embodiments of the inventive concepts described herein relate to a clock and data recovery device.
A clock and data recovery circuit is a device that restores a clock fit to a data rate from noisy data and samples data to restore it to refined data. The clock and data recovery circuit is an indispensable circuit in most data receivers. FIG. 1 is a block diagram schematically illustrating a conventional clock and data recovery device. In general, a clock and data recovery device consists of a phase detector 11, a charge pump unit 12, a loop filter unit 13, and a voltage controlled oscillator 14. Among phase detectors, a linear phase detector determines whether either of data clock and an output clock of the voltage controlled oscillator precedes and how fast either of the data clock and the output clock is, whereas it has a disadvantage in that it is difficult to operate at high speed. Among the phase detectors, a bang-bang phase detector can operate at high speed, but it only determines whether either of data clock and a output clock of the voltage controlled oscillator precedes. That is, the bang-bang phase detector can not determine how fast either of the data clock and the output clock is. A multi-level characteristic can be implemented using the bang-bang phase detector. However, as a number of level increases, a circuit area and power consumption increase.
On the other hand, production cost of a semiconductor circuit gradually decreases, but a cost needed to test the semiconductor circuit does not decrease. For example, a special comparator that operates at high speed and has high resolution is required to measure jitter of the semiconductor circuit. This causes an increase in a hardware cost and acts as a limitation in designing hardware. Also, a conventional jitter measurement device additionally necessitates a reference clock. For this reason, the conventional jitter measurement device is unsuitable in working together with a clock and data recovery device.